1. Field of the Invention
The invention relates in general to a method of fabricating semiconductor memory devices, and more particularly to a method of fabricating a DRAM cell by forming a capacitor electrode with cellular voids, to increase the capacitance by adding surface area.
2. Description of the Related Art
A dynamic random access memory (DRAM) is a widely used integrated circuit device, that presently plays an indispensable role in the electronics industry. FIG. 1 is a schematic diagram illustrating the circuit of a DRAM cell. As shown in FIG. 1, a memory cell consists of a transfer transistor T and a storage capacitor C. The source electrode of the transfer transistor T is coupled to a corresponding bit line BL, the drain electrode of the transfer transistor T is coupled to a storage electrode 6 of the storage capacitor and the gate electrode of the transfer transistor T is coupled to a corresponding word line WL. An opposed electrode 8 of the storage capacitor C is coupled to a fixed voltage source. A dielectric layer 7 is disposed between the storage electrode 6 and the opposed electrode 8. As known by those who are skilled in this art, the storage capacitor C used for storing data should have enough capacity to avoid the loss of data.
In a conventional process of fabricating a DRAM having a storage capacity of less than one mega-bits (1 MB), a two dimensional capacitance device, e.g. planar-type capacitor, is widely used for storing data. As shown in FIG. 2, where structures corresponding to those in FIG. 1 are designated with the same reference numbers, a field oxide layer 11 is formed on a substrate 10 to define an active region, and then a gate oxide layer 12, a gate electrode layer 13 and source-drain electrode regions 14 are formed in sequence to provide a transfer transistor T. On the surface of the substrate 10, which defines the storage electrode 6, a dielectric layer 7 and a conductive layer forming the opposed electrode 8 are formed adjacent to the drain electrode. The dielectric layer 7, the conductive layer 8 and the surface 6 of the substrate 10 where the layers 7 and 8 are formed, define a storage capacitor C. Obviously, a planar-type capacitor will occupy a fairly large area to form the storage capacitor C, which is inappropriate in a high integration DRAM.
Highly integrated DRAM, e.g. with a storage capacity of 4 MB and above, requires a three dimensional capacitance structure, such as in a "stack-type" capacitance device or a "trench-type" capacitance device, in order to realize its capacity.
FIG. 3 is a cross-sectional view of a conventional stack-type capacitance device, wherein structures corresponding to those in FIGS. 1 and 2 are designated by the same reference numbers. On a substrate 10, a field oxide layer 11, a gate oxide layer 12, a gate electrode layer 13 and source-drain electrode regions 14 are formed in sequence to construct a transfer transistor T. Next, an insulating layer 15 is formed, and a void is formed for a contact by etching the insulating layer above the source-drain electrode areas 14. Thereafter, a first polysilicon layer which is used as a storage electrode 6, a dielectric layer 7 and a second polysilicon layer which is used as an opposed electrode 8 are formed in sequence on the contact to complete a DRAM memory cell with the stack-type capacitor C. This memory cell can offer enough capacitance to assure the quality of device as the size of the device is diminished. However, when memory cells must be more highly integrated, such as in fabricating a DRAM with a storage capacity of 64 MB or greater, the above described simple structure of a stack-type capacitor is no longer appropriate.
FIG. 4 is a cross-sectional view of a conventional trench-type capacitor, wherein structures corresponding to those in FIGS. 1-3 are designated by the same reference numbers. First, a transfer transistor T is formed on a substrate 10 by an ordinary process, and includes a gate oxide layer 12, a gate electrode layer 13, and source-drain electrode regions 14. On the surface of the substrate 10, a deep trench is etched adjacent to the drain electrode. Next, within the deep trench, a storage capacitor C is formed. The storage capacitor C includes a dielectric layer 7, an opposed electrode 8 formed of a polysilicon layer, and a storage electrode 6 formed by the side wall of the substrate 10. This kind of capacitor structure can increase the surface area of the storage electrode, to raise the capacity of the capacitor. However, while the deep trench is being formed by etching, lattice defects are generated on the substrate, that increase leakage current and influence the characteristics of the device. Moreover, as the aspect ratio is increased, the etching rate is decreased, which adds difficulty to the process, and affects the efficiency of production.